This non-provisional application claims priority under 35 U.S.C. xc2xa7119 to Korean Patent Application No. 2002-0011345 filed Mar. 4, 2002, the contents of which are incorporated by reference in its entirety.
1. Field of the Invention
The present invention generally relates to the field of semiconductor devices. In particular, the present invention relates to a semiconductor memory device for reducing chip size by effectively arranging circuits for use in a semiconductor memory device that includes local input/output (I/O) lines and global I/O lines.
2. Description of the Related Art
With increases in the performance and integration density of semiconductor memory devices, efforts to reduce the chip area have been made not only on a process or circuit for manufacturing a semiconductor memory device but also in the field of circuit arranging methods, i.e., circuit layouts. The circuits used in a memory core are a repetition of identical circuits. As a result, the large layout of a certain circuit affects the entire chip size.
General dynamic random access memory (DRAM) uses local I/O lines and global I/O lines in order to achieve multiple input/output operations. A gating circuit composed of transistors is required to connect the local I/O lines to the global I/O lines. These transistors increase the layout of a memory device, thereby increasing the chip size.
Referring to FIGS. 1(a), 1(b) and 2, a conventional semiconductor device can best be seen. The conventional semiconductor memory device 100 is composed of a memory core and a gating circuit 140. The memory core is coupled between a bit line BL and a complementary bit line BLB, and includes a memory cell array 105, a bit line equalizer circuit 110, an isolation transistor 115, a PMOS sense amplifier (S/A) 120, a PMOS S/A driving circuit 125 for driving the PMOS S/A 120, a transmission gate circuit 130, an NMOS S/A 135, and an NMOS S/A driving circuit 145 for driving the NMOS S/A 135. The gating circuit 140 connects local I/O lines LIO and LIOB to global I/O lines GIO and GIOB.
The bit line equalizer circuit 110 is installed beside the memory cell array 105 and is followed by the isolation transistor 115 and the PMOS S/A 120. The PMOS S/A driving circuit 125 is installed next to the PMOS S/A 120. The PMOS S/A driving circuit 125 is a first driving transistor coupled between the PMOS S/A 120 and a supply voltage source (VCC). The transmission gate circuit 130 is installed beside the PMOS S/A driving circuit 125 and is followed by the gating circuit 140. The gating circuit 140 includes two transistors, MN1 and MN2, for connecting the local I/O lines LIO and LIOB to the global I/O lines GIO and GIOB. The NMOS S/A driving circuit 145 and the NMOS S/A 135 are installed beside the gating circuit 140. The NMOS S/A driving circuit 145 is an NMOS transistor coupled between the NMOS S/A 135 and a circuit ground. The isolation transistor 15 and the bit line equalizer circuit 110 are installed next to the NMOS S/A 135.
Because the structure and operation of each of the aforementioned circuits are generally known to those ordinarily skilled in the art, they will not be described in detail.
Referring now to FIGS. 1(a) and (b), it can be seen that the transistors MN1 and MN2 of the gating circuit 140 enlarge the layout of the conventional semiconductor memory device 100 toward the memory cell array 105. It can also be seen that the layout of the conventional semiconductor memory device 100 is enlarged toward the memory cell array 105 by the installation of the PMOS S/A driving circuit 125 and the NMOS S/A driving circuit 145. Such an enlargement of the semiconductor memory device 100 occurs because the transistors MN1 and MN2 of the gating circuit 140, or the transistors of the PMOS and NMOS S/A driving circuits 125 and 145, are installed perpendicular to the bit line BL. In particular, the MN1 transistors MN1 and MN2 of the gating circuit 140, or the transistors of the PMOS and NMOS S/A driving circuits 125 and 145, are installed in such a way that their gates are perpendicular to the bit line BL. In FIG. 1(b) the gates of the transistors MN1 and MN2 are installed perpendicular to the bit line BL. Accordingly, the transistors MN1 and MN2 of the gating circuit 140 or the transistors of the PMOS and NMOS S/A driving circuits 125 and 145 increase the chip area of a semiconductor memory device by a large percentage.
At least one exemplary embodiment of the present invention provides a semiconductor memory device that is prevented from having an increased chip size due to the conventional layout of a gating circuit for connecting local input/output (I/O) lines to global I/O lines and the conventional layouts of PMOS and NMOS sense amplifier driving circuits.